The Zedboard’s device name is Z-7020; and if we take a look at the data sheet of the Zynq-7000, we can find that the Block RAM size is 4.9Mb, or 140 x 36Kb blocks of BRAM.
FIFO can be used as a bridge between the PS and PL, as either will have different frequencies. To prevent data loss, the FIFO is used as a shared buffer as a synchronization circuit. (Ref)
chpresearch 
On the Zedboard there are 280 BRAM_18K of size 18Kbits. So, 280 x 18 = 5040 Kbits = 5040/1024 = 4.92 Mbits.
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Thanks for the breakdown!
On Table 1 of the reference, it states
140 “Block RAM (# of 36 Kb blocks)”
Also, on page 2, under “Programmable Logic (PL)”, a 36Kb Block RAM is described to be “True Dual-port”, and “configurable as a dual 18Kb block RAM”. (also up to 72 bits wide; I’m guessing the width of each port? or is it the sum of both ports?)
So as a 36kB BRAM can be configured as a dual 18Kb BRAM, we can assume to have 280 18kB BRAMs!
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For details refer to Page 25, the paragraph starting with: “Each Block RAM …”:
Click to access The_Zynq_Book_ebook.pdf
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