Driving FPGA IPs from Linux

 few links that’ll help me get started:

Zedboard.org forum

http://fpgacpu.wordpress.com/2013/05/24/yet-another-guide-to-running-linaro-ubuntu-desktop-on-xilinx-zynq-on-the-zedboard/

http://fpgacpu.wordpress.com/2013/05/28/how-to-design-and-access-a-memory-mapped-device-part-one/

http://fpgacpu.wordpress.com/2013/05/28/how-to-design-and-access-a-memory-mapped-device-part-two/

Forum Posts:

http://zedboard.com/content/how-communicate-fpga-linux

http://zedboard.org/content/interrupt-handler-kernel-module

By Sven Andersson

http://svenand.blogdrive.com/archive/203.html

Xilinx Wiki code

http://www.wiki.xilinx.com/Linux+User+Mode+Pseudo+Driver

Generating DTS and DTIs from Xilinx SDK

Xilinx Tutorial

DTB compiling help

When building the kernel with the uImage we need a mkimage which is in the uboot. Also uboot requires dtc which is available on the Fetch sources.

At the moment the kernel doesn’t boot after Starting kernel ...

Building the Kernel

The Xilinx manual makes the kernel load at 0x208000 however the u-boot boots from 0x8000; thus changed the

make ARCH=arm xilinx_zynq_defconfig
make ARCH=arm menuconfig
make ARCH=arm uImage LOADADDR=0x00008000

Also, changed the linux-xlnx branch from master to the xilinx-v2016.2 tag.

More problems: Nice forum post

https://forums.xilinx.com/t5/Embedded-Linux/Zynq-Linux-Freeze-on-Memory-Mapped-Peripheral-Write/td-p/246156

This post was helpful. It first identified that a problem may be in the FSBL

From the u-boot if the following command does not work, then we may need to recompile the FSBL

md.l 0x43c00000

If this does not work, the translation table in the FSBL must be incorrect. (This may be because we use the UCR-Bar’s files.Build the FSBL with the boot.bif in the UCR-Bar repo.

This page tells us how to create the FSBL Boot image, and This page how to build the FSBL from our IP configuration.

Done! – The process

• Thus we need to create a FSBL that allows us to access the actual physical addresses that are mapped for the IP.
  • FSBL is created by the SDK (new project (standalone) -> FSBL(template))
  • Package the FSBL and bitstream into a Boot.bin by using the `bootgen` tool and refer to [boot.bif](https://github.com/ucb-bar/fpga-images-zedboard/blob/968b9dd258c2dfef2d9108335889b993737f5650/boot.bif) file.
• Our device tree needs to map the IP address for the UIO
• [Enable the FPGA clk](https://forums.xilinx.com/t5/Embedded-Linux/Zynq-Linux-Freeze-on-Memory-Mapped-Peripheral-Write/m-p/685323#M15566) on the device tree